1. Field of the Invention
The present invention relates generally to a method for generating a preamble set or group in a communication system and an apparatus adopting the method, and in particular, to a method for generating an optimal preamble set using a plurality of sequences used to increase the limited number of channels, and an apparatus adopting the method.
2. Description of the Related Art
Generally, communication systems support communication services and include transmitters and receivers.
FIG. 1 is a block diagram of a general communication system. Referring to FIG. 1, a transmitter 10 and a receiver 20 provide communication services using frames. The transmitter 10 and the receiver 20 need to acquire synchronization information for accurate transmission and reception of the frames.
In order to acquire the synchronization information of the receiver 20, the transmitter 10 transmits to the receiver 20 a synchronization signal indicating the start position of a frame transmitted to the receiver 20. Upon receiving the synchronization signal and the frame transmitted from the transmitter 10, the receiver 20 detects the start position of the received frame, i.e. frame timing, using the received synchronization signal. The receiver 20 demodulates the received frame using the detected frame timing. A specific preamble sequence, which has been previously agreed upon between the transmitter 10 and the receiver 20, is used as the synchronization signal.
Various methods such as the use of a preamble or a pilot signal are used to acquire synchronization with transmitted frames in communication systems. In the case of acquiring synchronization using a preamble as mentioned above, it is a general practice to use a single preamble.
FIG. 2 illustrates a frame structure used in the general communication system. As shown in FIG. 2, a frame is composed of a preamble 30 and data 40. The preamble 30 is used for frame synchronization and channel estimation. The data 40 includes data selected and requested by a user for transmission and/or control information of the communication system.
The frame structure may have a fixed format according to the communication system as shown in FIG. 2, but in other communication systems, the preamble 30 may be positioned in the middle of or at the end of the data 40. In other words, a preamble in a frame may be positioned differently according to communication systems.
The preamble 30 shown in FIG. 2 is comprised of a first signal 32 and a second signal 34. The first signal 32 is used for frame synchronization and the second signal 34 is used for channel estimation. The structure of the preamble 30 shown in FIG. 2 can be formed by divided into two parts, i.e. the first signal 32 and the second signal 34, but may also be formed repetitively using a single signal or using several concatenated signals without dividing into two parts. In some communication systems, the first signal 32 is divided into two parts: one for frame synchronization and the other for packet synchronization.
FIG. 3 is a block diagram of a transmitter for the general communication system.
A data creator 51 receives data, creates transmission data, and transmits the created transmission data to a first multiplexer 54. A media access control (MAC) header creator 52 creates a MAC header suitable for frames and transmits the created MAC header to the first multiplexer 54. A physical (PHY) header creator 53 creates a PHY header suitable for the communication system and transmits the created PHY header to the first multiplexer 54. The first multiplexer 54 multiplexes, i.e. mixes signals transmitted from the data creator 51, the MAC header creator 52, and the PHY header creator 53, and transmits a resultant signal to a second multiplexer 57. The resultant signal is referred to as transmission data.
A preamble creator 56 creates a preamble suitable for the communication system and transmits the created preamble to the second multiplexer 57. The transmission data multiplexed by the first multiplexer 54 and the preamble created by the preamble creator 56 are input to the second multiplexer 57. The second multiplexer 57 combines the transmission data from the first multiplexer 54 with the preamble from the preamble creator 56 to convert them into a transmission frame, and transmits the transmission frame to a receiver side through a transmission antenna 58.
FIG. 4 is a block diagram of a receiver for the general communication system. Referring to FIG. 4, the frame transmitted from the transmitter of FIG. 3 is received through a reception antenna 61. The frame received through the reception antenna 61 is sent to a preamble analyzer 62 and a demultiplexer 63. The preamble analyzer 62 analyzes the preamble in the received frame and detects synchronization information and channel estimation information. The preamble analyzer 62 determines the start position of the received frame using the synchronization information and the channel estimation information.
When the start point of the received frame is detected, the demultiplexer 63 separates the PHY header, the MAC header, and the data from the transmission data of the received frame with reference to the start position of the received frame. The separated signals are input to a PHY header analyzer 64, an MAC header analyzer 65, and a data restorer 66.
The PHY header analyzer 64 analyzes the PHY header transmitted from the demultiplexer 63 and transmits the result of the header analysis to the data restorer 66. The MAC header analyzer 65 analyzes the MAC header transmitted from the demultiplexer 63 and transmits the result of the header analysis to the data restorer 66. The data restorer 66 restores the data transmitted from the demultiplexer 63 using the results of the header analysis transmitted from the PHY header analyzer 64 and the MAC header analyzer 65.
The preamble sequence, which is agreed upon between the transmitter and the receiver of the communication system, may vary from system to system, but an aperiodic recursive multiplex (ARM) sequence will be used as the preamble sequence herein as an example. The preamble sequence that can be applied to the present invention is not limited to the ARM sequence, and may include any possible sequences that can be used as preambles. The ARM sequence exhibits superior auto-correlation in an aperiodic environment where sequences are not periodically transmitted.
Superior auto-correlation indicates that auto-correlation is high when the sequences are synchronized and auto-correlation is relatively low in other cases.
FIG. 5 is a block diagram of an ARM sequence generation apparatus that can generate an ARM sequence of a length 128. As shown in FIG. 5, when one of the possible 2-bit combinations of real numbers (‘00’, ‘01’, ‘10’, or ‘11’) is input as an input signal, the input signal is also input to a first multiplexer 81. The input signal is input to a first XOR operator 71.
At the same time, a first signal generator 91 generates a signal ‘01’ or ‘10’ and outputs the generated signal to the first XOR operator 71. The first XOR operator 71 performs an exclusive or operation on the signal output from the first signal generator 91 and the input signal, and outputs a result of the XOR operation to the first multiplexer 81. The first multiplexer 81 alternatively multiplexes the input signal and a signal output from the first XOR operator 71 and creates an ARM sequence of 4 bits. The first multiplexer 81 outputs the created 4-bit ARM sequence to a second multiplexer 82 and a second XOR operator 72.
A second signal generator 92 generates a signal ‘0101’ or ‘1010’ and outputs the generated signal to the second XOR operator 72 at the same time that the 4-bit ARM sequence is input to the second multiplexer 82 from the first multiplexer 81. The second XOR operator 72 performs an XOR operation on the signal output from the second signal generator 92 and the 4-bit ARM sequence output from the first multiplexer 81, and outputs a result of the XOR operation to the second multiplexer 82. The second multiplexer 82 alternatively multiplexes the signal output from the first multiplexer 81 and the signal output from the second XOR operator 72 to create an ARM sequence of 8 bits and outputs the created 8-bit ARM sequence to a third multiplexer 83 and a third XOR operator 73.
A third signal generator 93 generates a signal ‘01010101’ or ‘10101010’ and outputs the generated signal to the third XOR operator 73 at the same time that the 8-bit ARM sequence is input to the third multiplexer 83 from the second multiplexer 82. The third XOR operator 73 performs an XOR operation on the signal output from the third signal generator 93 and the 8-bit ARM sequence output from the second multiplexer 82, and outputs a result of the XOR operation to the third multiplexer 83. The third multiplexer 83 alternatively multiplexes the signal output from the second multiplexer 82 and the signal output from the third XOR operator 73 to create an ARM sequence of 16 bits and outputs the created 16-bit ARM sequence to a fourth multiplexer 84 and a fourth XOR operator 74.
A fourth signal generator 94 generates a signal ‘0101010101010101’ or ‘1010101010101010’ and outputs the created signal to the fourth XOR operator 74 at the same time that the 16-bit ARM sequence is input to the fourth multiplexer 84 from the third multiplexer 83. The fourth XOR operator 74 performs an XOR operation on the signal output from the fourth signal generator 94 and the 16-bit ARM sequence output from the third multiplexer 83, and outputs a result of the XOR operation to the fourth multiplexer 84. The fourth multiplexer 84 alternatively multiplexes the signal output from the third multiplexer 83 and the signal output from the fourth XOR operator 74 to create an ARM sequence of 32 bits, and outputs the created 32-bit ARM sequence to a fifth multiplexer 85 and a fifth XOR operator 75.
A fifth signal generator 95 generates a signal ‘01010101010101010101010101010101’ or ‘10101010101010101010101010101010’ and outputs the created signal to the fifth XOR operator 75 at the same time that the 32-bit ARM sequence is input to the fifth multiplexer 85 from the fourth multiplexer 84. The fifth XOR operator 75 performs an XOR operation on the signal output from the fifth signal generator 95 and the 32-bit ARM sequence output from the fourth multiplexer 84 and outputs a result of the XOR operation to the fifth multiplexer 85. The fifth multiplexer 85 alternatively multiplexes the signal output from the fourth multiplexer 84 and the signal output from the fifth XOR operator 75 to create an ARM sequence of 64 bits and outputs the created 64-bit ARM sequence to a sixth multiplexer 86 and a sixth XOR operator 76.
A sixth signal generator 96 generates a signal ‘010101010101010101010101010101011010101010101010101010101010101’ or ‘1010101010101010101010101010101010101010101010101010101010101010’ and outputs the created signal to the sixth XOR operator 76 at the same time that the 64-bit ARM sequence is input to the sixth multiplexer 86 from the fifth multiplexer 85. The sixth XOR operator 76 performs an XOR operation on the signal output from the sixth signal generator 96 and the 64-bit ARM sequence output from the fifth multiplexer 85, and outputs a result of the XOR operation to the sixth multiplexer 86. The sixth multiplexer 86 alternatively multiplexes the signal output from the fifth multiplexer 85 and the signal output from the sixth XOR operator 76 to create an ARM sequence of 128 bits.
The created 128-bit ARM sequence is used for detecting frame synchronization in the preamble analyzer 62 of FIG. 4. The length of the ARM sequence is extendable by powers of 2 such as 64, 128, 256, 512, and the like. Since the ARM sequence is produced from a plurality of inputs, the number of sequences of the ARM sequence is equal to two times the length of the ARM sequence. For example, the 128-bit ARM sequence shown in FIG. 5 has a total of 256 (=128*2) sequences.
Conventional preamble signals are only used for detection of frame synchronization and channel estimation in receivers of communication systems.